CMOS High Efficiency On-chip Power Management (Analog by John Hu

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By John Hu

This ebook will introduce a variety of strength administration built-in circuits (IC) layout options to construct destiny energy-efficient “green” electronics. The objective is to accomplish excessive potency, that's necessary to meet shoppers’ growing to be want for longer battery lives. the focal point is to check topologies amiable for complete on-chip implementation (few exterior elements) within the mainstream CMOS know-how, on the way to decrease the actual measurement and the producing rate of the units.

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Extra resources for CMOS High Efficiency On-chip Power Management (Analog Circuits and Signal Processing)

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8). Quantitatively, the amount of DC line regulation can be defined and calculated using Fig. 9. 8) Let AEA , APT be the DC gain of the error amplifier and the PMOS pass element respectively. 12) As a result, a higher error amplifier gain, which is part of the DC loop gain, improves the line regulation. 2 LDO Performance and Design Challenges 47 ID VSG2=VSG,max P3 Iload,2=Iload,max P0 Iload Iload,1 VSG0 VSG1 P4 Req VDO VSD Fig. 10 Qualitative analysis of DC load regulation using PMOS I-V curve factors such as the DC line regulations of the error amplifier or voltage reference, or the op-amp input offset voltages, all of which could introduce additional error.

To comprehensively model the leakage-supply relation, experimental data from a 65 nm ultra-low-power CMOS SRAM design (Wang et al. 2008) is used to construct an empirical formula. As seen in Fig. 8 curve (a), the total leakage per bit decreases almost linearly with VDD in the logarithm scale, which is in agreement with the exponential VDD relationship of Isub , which is supposed to be dominant. Though additional techniques like PMOS back gate bias (b) and virtual ground raise (c) would reduce the leakage further as reported in Wang et al.

5V) in Wang et al. 38. 5) The comparison is made between the conventional LDO based power chain and the proposed DC-DC converter, as seen in Fig. 9. 6) The DC/DC converter is assumed to have efficiency of η . 10 shows the battery currents of the resulting system during sleep mode. 9 V. This is because an ideal LDO’s efficiency improves as the drop-out voltage is reduced (This will be discussed further in Chap. 3), but DC-DC converter is assumed to have a flat 30% efficiency in this case. 2 Very Low Power Applications: A Sleep Mode Perspective a VBAT T = 3V 29 bV BAT T = 3V ILEAK IBAT T ≈ VηDDVBAT T IBAT T ≈ ILEAK η = 30%; 60%; 90% VDD VDD ILEAK = f(VDD) ILEAK = f(VDD) 8KB RAM data retention 8KB RAM data retention IQ ≈ 0 Ideal LDO DC/DC Fig.

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