By Thucydides Xanthopoulos
The aim of Clocking in glossy VLSI structures is to supply a concise exposition of all significant matters in clocking huge state of the art microprocessors and SoCs. the problems coated contain clock new release and distribution, clocking parts, testability, substitute clocking types, distinct suggestions, and working with scaling and strategy edition. This e-book offers extensive insurance of a few of the themes through recognized specialists in and academia and should function an invaluable reference for working towards VLSI engineers, technical managers, and complex graduate scholars.
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Extra resources for Clocking in Modern VLSI Systems (Integrated Circuits and Systems)
26. 4 Microprocessor Clock Distributions Due to the design complexity and the significant mis-tracking to process, voltage and temperature, a fully unconstrained clock distribution network is rarely (if ever) applied to a processor design. The closest example is a hybrid combination of symmetric and asymmetric clock trees. 27 shows an example of a processor clock distribution with a first level H-tree connected to multiple secondary trees that are asymmetric but delay balanced. Fig. 27. Asymmetric clock tree distribution network based on delay matching.
Each DSK cluster may contain up to four independent deskew buffers. a b DSK DSK DSK DSK DSK DSK DSK DSK CDC PLL DSK DSK DSK DSK DSK DSK DSK DSK DSK = Cluster of 4 deskew buffers CDC = Central Deskew Controller Fig. 39. Deskew zones in the itanium R processor. Reproduced with permission from , c 2000 IEEE 11 Other names and brands may be claimed as property of others. 40 shows the detailed clock distribution architecture of  that encompasses the H-tree global distribution, the grid structure for the regional distribution, and the local buffers for the local distribution.
G. local flip-flops). A processor will have a large number of these local points and will require a large number of branches and therefore a deep distribution tree. A deep distribution tree will exhibit large POD delays and degraded clock performance. Subdividing the die into a smaller number of clock regions and applying a grid to serve each region can be a superior solution. 22 schematically shows a 2-dimensional grid serving one of these clock regions. This clock grid resembles a mesh with fully connected clock tracks in both dimensions and grid drivers located on all four sides.